The coordinate system

The CPU Technology Ontology

These dimensions name the irreducible questions every CPU technology answers: what machine it promises to software, how it moves bits, how it controls time, where memory lives, how it multiplies work, what physical envelope it inhabits, and what evidence lets us understand it.

ISA - What instruction vocabulary, state model, and compatibility burden define the machine?

ISA Contract

A CPU first exists as an architectural contract: opcodes, registers, memory model, exceptions, privilege, and compatibility rules that software can rely on.

software-visible state + instructions + ordering rules = architectural machine

ISA Family

x86 / CISC RISC Microcontroller ISA DSP / Vector Open ISA

Compatibility Burden

Clean Slate Lineage Bound Extension Layered

DP - What width, registers, ALUs, shifters, multipliers, and buses carry computation?

Datapath

The datapath is the CPU's working body: register files, execution units, internal buses, operand paths, bypasses, and result writeback.

operands -> functional units -> results -> architectural state

Word Width

4/8-bit 16/32-bit 64-bit Vector Wide

State Shape

Accumulator Register File Renamed Physical Registers Stack / Windowed

CU - Is sequencing hardwired, microcoded, predicted, speculative, or dynamically scheduled?

Control Unit

Control turns instruction meaning into timed internal action: fetch, decode, sequencing, hazards, traps, branch decisions, and speculation.

instruction meaning + machine state -> next micro-actions

Sequencing

Hardwired Microcoded Decoded uops Dynamic Scheduler

Future Handling

Direct Branch Static Prediction Dynamic Prediction Deep Speculation

EX - Does the CPU execute sequentially, pipeline stages, issue multiple operations, or reorder around stalls?

Execution Organization

Execution organization defines the temporal shape of work: multi-cycle sequencing, pipelines, superscalar issue, out-of-order windows, VLIW bundles, and SIMD lanes.

latency is not throughput once work can overlap

Overlap Form

Multi-Cycle Scalar Pipeline Superscalar Out-of-Order VLIW / SIMD

Hazard Discipline

Software Visible Interlocked Forwarded Renamed

MEM - What hierarchy stands between execution units and memory?

Memory System

CPU behavior depends on locality: registers, caches, TLBs, buses, memory controllers, coherence, and DRAM latency.

near data is cheap; far data shapes the whole machine

Hierarchy

Direct Memory L1 Only Private L2 Shared Last-Level Cache Scratchpad / Local Store

Coherence

Single Core Snooping Directory Heterogeneous Memory

PAR - Is parallel work inside an instruction, inside a core, across cores, or across specialized blocks?

Parallelism Topology

CPU technology scales through lanes, issue slots, hardware threads, cores, chiplets, accelerators, and interconnect rather than through one bigger ALU alone.

parallelism appears as lanes, slots, threads, cores, clusters, and fabrics

Multiplicity

Scalar Superscalar Core SIMD / Vector SMT Multicore Heterogeneous

Fabric

Single Bus Ring / Mesh Chiplet

PHY - How do process, transistor budget, packaging, clocking, and fabrication constraints shape the design?

Physical Implementation

CPUs are physical devices: NMOS, CMOS, bipolar, bit-slice boards, ASICs, FPGAs, chiplets, and SoCs each make different tradeoffs possible.

technology node + transistor budget + package + clocking = feasible architecture

Fabrication

Board Level Classic NMOS/CMOS Deep Submicron FinFET / Advanced Node FPGA / Softcore

Clocking

Single Clock Multi-Domain DVFS

PWR - Is the design bounded by batteries, cooling, leakage, determinism, or datacenter throughput per watt?

Power and Thermal Regime

Power governs clock speed, leakage, boost behavior, sustained performance, mobile design, embedded duty cycles, and server economics.

performance is constrained by energy per operation and heat removal

Envelope

Ultra-Low Power Embedded Deterministic Desktop Thermal Mobile SoC Server Throughput

SYS - Is the CPU the central computer, an embedded controller, a signal processor, a console chip, or one block in a heterogeneous SoC?

System Role

The same architectural mechanisms mean different things when the CPU is a desktop heart, a microcontroller, a DSP, or a phone SoC cluster.

a CPU's identity is partly its job in the system

Role

General Purpose Embedded Control Signal Processing Game / Console SoC Cluster Server Node

EV - Which measurements, manuals, simulations, and benchmark traces can support claims about the processor?

Evidence Layer

The model corpus belongs here: it is evidence about CPUs, not the object of the ontology. It records how well each processor is known.

claims about CPUs inherit the limits of their evidence

Evidence Status

Validated Standard Validated Limited Architectural Estimate Flagged

Source Mode

Silicon Measured Manual Derived Benchmark Inferred Simulated