Evidence Layer - Evidence Status
Architectural Estimate
Known structure gives a plausible account without full validation.
CPU Exemplars With This Coordinate
Intel 4004
1971 - intel
A 4-bit microprocessor showing the CPU as a new integrated control object: narrow datapath, small state, external memory, and board-level system role.
ARCHITECTURAL_ESTIMATEARM7TDMI
1994 - arm
A compact RISC core where clean ISA structure, scalar pipeline, and low-power embedded use define the technology more than peak throughput.
ARCHITECTURAL_ESTIMATEMIPS R4000
1991 - mips
A 64-bit RISC workstation/server CPU that makes clean load-store design, deep pipelining, and cache hierarchy visible as technology choices.
ARCHITECTURAL_ESTIMATEIntel Pentium 4 Northwood
2002 - intel
The deep-pipeline frequency wager: a CPU technology organized around high clocks, aggressive prediction, and large penalties for wrong futures.
ARCHITECTURAL_ESTIMATEApple M1
2020 - apple
A mobile-derived SoC CPU complex where high-performance cores, efficiency cores, unified memory, media blocks, and power policy form one technology object.
ARCHITECTURAL_ESTIMATEAMD EPYC Rome
2019 - amd
A chiplet-era server CPU where cores, cache slices, IO die, memory channels, and package fabric define the processor as a distributed object.