ISA Contract - ISA Family
RISC
Regular load/store instruction sets built for simple decode, pipelining, and compiler-visible structure.
CPU Exemplars With This Coordinate
ARCHITECTURAL_ESTIMATE
ARM7TDMI
1994 - arm
A compact RISC core where clean ISA structure, scalar pipeline, and low-power embedded use define the technology more than peak throughput.
ARCHITECTURAL_ESTIMATEMIPS R4000
1991 - mips
A 64-bit RISC workstation/server CPU that makes clean load-store design, deep pipelining, and cache hierarchy visible as technology choices.
ARCHITECTURAL_ESTIMATEApple M1
2020 - apple
A mobile-derived SoC CPU complex where high-performance cores, efficiency cores, unified memory, media blocks, and power policy form one technology object.