Execution Organization - Overlap Form

Scalar Pipeline

One instruction enters per cycle while stages overlap.

CPU Exemplars With This Coordinate

ARCHITECTURAL_ESTIMATE

ARM7TDMI

1994 - arm

A compact RISC core where clean ISA structure, scalar pipeline, and low-power embedded use define the technology more than peak throughput.

 VALIDATED_LIMITED

Intel i80486

1989 - intel

A mainstream x86 CPU where compatibility, pipelining, on-chip cache, and integrated floating point converge into the modern desktop processor shape.

 ARCHITECTURAL_ESTIMATE

MIPS R4000

1991 - mips

A 64-bit RISC workstation/server CPU that makes clean load-store design, deep pipelining, and cache hierarchy visible as technology choices.