PHY · CPU ontology dimension

Physical Implementation

CPUs are physical devices: NMOS, CMOS, bipolar, bit-slice boards, ASICs, FPGAs, chiplets, and SoCs each make different tradeoffs possible.

technology node + transistor budget + package + clocking = feasible architecture

Fabrication

Board Level

The CPU function is assembled from multiple chips or bit-slices.

Classic NMOS/CMOS

Early integrated microprocessors constrained by area, pins, and bus timing.

Deep Submicron

High-frequency CMOS enables larger caches, prediction, and out-of-order structures.

FinFET / Advanced Node

Density and energy constraints favor large SoCs, chiplets, and specialized blocks.

FPGA / Softcore

The CPU is configured into programmable fabric rather than fabricated as fixed silicon.

Clocking

Single Clock

One main clock domain governs most CPU behavior.

Multi-Domain

Cores, uncore, memory, or accelerators run in distinct domains.

DVFS

Voltage and frequency shift dynamically to match power, thermal, and workload conditions.