ISA Contract - ISA Family
x86 / CISC
Dense, historically layered instruction contracts with complex decode and deep backward compatibility.
CPU Exemplars With This Coordinate
Intel i80486
1989 - intel
A mainstream x86 CPU where compatibility, pipelining, on-chip cache, and integrated floating point converge into the modern desktop processor shape.
VALIDATED_LIMITEDIntel Pentium Pro
1995 - intel
A hinge point for x86: instructions become internal uops, speculation becomes central, and the CPU starts behaving like a dynamic scheduling machine.
ARCHITECTURAL_ESTIMATEIntel Pentium 4 Northwood
2002 - intel
The deep-pipeline frequency wager: a CPU technology organized around high clocks, aggressive prediction, and large penalties for wrong futures.
ARCHITECTURAL_ESTIMATEAMD EPYC Rome
2019 - amd
A chiplet-era server CPU where cores, cache slices, IO die, memory channels, and package fabric define the processor as a distributed object.