Representative processors
CPU Exemplars
A curated set of processors from the source corpus, chosen because each makes a different technological question visible.
Intel 4004
1971 - intel - models/intel/intel_4004
A 4-bit microprocessor showing the CPU as a new integrated control object: narrow datapath, small state, external memory, and board-level system role.
ARCHITECTURAL_ESTIMATEARM7TDMI
1994 - arm - models/arm/arm7tdmi
A compact RISC core where clean ISA structure, scalar pipeline, and low-power embedded use define the technology more than peak throughput.
VALIDATED_LIMITEDIntel i80486
1989 - intel - models/intel/i80486
A mainstream x86 CPU where compatibility, pipelining, on-chip cache, and integrated floating point converge into the modern desktop processor shape.
ARCHITECTURAL_ESTIMATEMIPS R4000
1991 - mips - models/mips/mips_r4000
A 64-bit RISC workstation/server CPU that makes clean load-store design, deep pipelining, and cache hierarchy visible as technology choices.
VALIDATED_LIMITEDIntel Pentium Pro
1995 - intel - models/intel/pentium_pro
A hinge point for x86: instructions become internal uops, speculation becomes central, and the CPU starts behaving like a dynamic scheduling machine.
ARCHITECTURAL_ESTIMATEIntel Pentium 4 Northwood
2002 - intel - models/intel/pentium_4_northwood
The deep-pipeline frequency wager: a CPU technology organized around high clocks, aggressive prediction, and large penalties for wrong futures.
VALIDATED_LIMITEDIntel Skylake i7-6700K
2015 - intel - models/intel/skylake_i7_6700k
A mature client CPU: wide out-of-order cores, layered caches, SIMD extensions, aggressive power management, and system fabric as part of the processor identity.
ARCHITECTURAL_ESTIMATEApple M1
2020 - apple - models/apple/apple_m1
A mobile-derived SoC CPU complex where high-performance cores, efficiency cores, unified memory, media blocks, and power policy form one technology object.
ARCHITECTURAL_ESTIMATEAMD EPYC Rome
2019 - amd - models/amd/amd_epyc_rome
A chiplet-era server CPU where cores, cache slices, IO die, memory channels, and package fabric define the processor as a distributed object.