A first-principles ontology of CPU technology
CPUs as Technological Objects
A sub-atlas for processors themselves: ISA contracts, datapaths, control units, execution organization, memory systems, parallelism, physical implementation, power envelopes, system roles, and the evidence used to understand them.
Ontology Spine
ISAISA Contract
What promise does the CPU make to software?
DPDatapath
Where do bits physically move and transform?
CUControl Unit
How does the CPU decide what happens next?
EXExecution Organization
How much work can be overlapped inside the core?
MEMMemory System
How far away is the data?
PARParallelism Topology
Where does multiplicity live?
PHYPhysical Implementation
What kind of artifact is this CPU in matter?
PWRPower and Thermal Regime
What envelope must the CPU live inside?
SYSSystem Role
What larger machine is the CPU serving?
EVEvidence Layer
How do we know what the CPU is doing?
CPU Exemplars
Intel 4004
1971 - intel
A 4-bit microprocessor showing the CPU as a new integrated control object: narrow datapath, small state, external memory, and board-level system role.
ARCHITECTURAL_ESTIMATEARM7TDMI
1994 - arm
A compact RISC core where clean ISA structure, scalar pipeline, and low-power embedded use define the technology more than peak throughput.
VALIDATED_LIMITEDIntel i80486
1989 - intel
A mainstream x86 CPU where compatibility, pipelining, on-chip cache, and integrated floating point converge into the modern desktop processor shape.
ARCHITECTURAL_ESTIMATEMIPS R4000
1991 - mips
A 64-bit RISC workstation/server CPU that makes clean load-store design, deep pipelining, and cache hierarchy visible as technology choices.
VALIDATED_LIMITEDIntel Pentium Pro
1995 - intel
A hinge point for x86: instructions become internal uops, speculation becomes central, and the CPU starts behaving like a dynamic scheduling machine.
ARCHITECTURAL_ESTIMATEIntel Pentium 4 Northwood
2002 - intel
The deep-pipeline frequency wager: a CPU technology organized around high clocks, aggressive prediction, and large penalties for wrong futures.
Evidence Layer From modeling_2026
Validated Standard
The source evidence for this CPU is strong enough to support detailed quantitative use.
Validated Limited
The CPU has at least one useful held-out evidence chain, but the quantitative picture remains bounded.
Architectural Estimate
The CPU structure is represented, but independent quantitative validation is incomplete.
Flagged
The source evidence has an invariant or audit issue; use it as a prompt for repair, not settled evidence.