ISA · CPU ontology dimension
ISA Contract
A CPU first exists as an architectural contract: opcodes, registers, memory model, exceptions, privilege, and compatibility rules that software can rely on.
ISA Family
x86 / CISC
Dense, historically layered instruction contracts with complex decode and deep backward compatibility.
RISC
Regular load/store instruction sets built for simple decode, pipelining, and compiler-visible structure.
Microcontroller ISA
Small embedded contracts optimized for control, interrupts, and deterministic peripheral interaction.
DSP / Vector
Contracts that expose multiply-accumulate, packed lanes, or stream-oriented operations.
Open ISA
Architectures such as RISC-V where the contract is extensible and public by design.
Compatibility Burden
Clean Slate
The CPU can optimize around a relatively new or narrow software contract.
Lineage Bound
The CPU inherits earlier modes, encodings, or behavioral quirks.
Extension Layered
The base ISA grows through optional vector, crypto, floating-point, or privilege extensions.