MEM · CPU ontology dimension
Memory System
CPU behavior depends on locality: registers, caches, TLBs, buses, memory controllers, coherence, and DRAM latency.
near data is cheap; far data shapes the whole machine
Hierarchy
Direct Memory
The CPU largely waits on main memory or external bus timing.
L1 Only
A small on-chip cache captures common locality but misses fall far.
Private L2
A second near level filters misses before shared fabric or DRAM.
Shared Last-Level Cache
Multiple cores rely on a shared L3 or system cache.
Scratchpad / Local Store
Software manages explicit fast memory rather than relying on transparent cache.
Coherence
Single Core
No inter-core coherence is needed.
Snooping
Cores observe shared-bus traffic to keep caches coherent.
Directory
A directory tracks ownership and sharing across larger systems.
Heterogeneous Memory
CPU, GPU, accelerators, or devices share memory with special ordering and visibility rules.