intel - 1989 - evidence: VALIDATED_LIMITED

Intel i80486

A mainstream x86 CPU where compatibility, pipelining, on-chip cache, and integrated floating point converge into the modern desktop processor shape.

Evidence source: martingallagher-code/modeling_2026/models/intel/i80486

Technology Coordinates

Dimension	Value	Meaning
ISA Contract	x86 / CISC	Dense, historically layered instruction contracts with complex decode and deep backward compatibility.
Datapath	16/32-bit	General-purpose scalar datapaths broad enough for operating systems and richer address spaces.
Control Unit	Microcoded	Complex instructions are broken into internal micro-operations or control-store steps.
Execution Organization	Scalar Pipeline	One instruction enters per cycle while stages overlap.
Memory System	L1 Only	A small on-chip cache captures common locality but misses fall far.
Parallelism Topology	Scalar	One main stream of work dominates the processor.
Physical Implementation	Classic NMOS/CMOS	Early integrated microprocessors constrained by area, pins, and bus timing.
Power and Thermal Regime	Desktop Thermal	Boost and cooling determine how long peak clocks can be sustained.
System Role	General Purpose	Runs operating systems and varied applications.
Evidence Layer	Validated Limited	Useful evidence exists, but coverage is limited.

Backward compatibility becomes a physical design burden.

On-chip cache changes the CPU from a bus-paced device to a locality-dependent machine.

The desktop CPU is a negotiated artifact between software inheritance and new silicon capacity.