arm - 1994 - evidence: ARCHITECTURAL_ESTIMATE

ARM7TDMI

A compact RISC core where clean ISA structure, scalar pipeline, and low-power embedded use define the technology more than peak throughput.

Evidence source: martingallagher-code/modeling_2026/models/arm/arm7tdmi

Technology Coordinates

Dimension	Value	Meaning
ISA Contract	RISC	Regular load/store instruction sets built for simple decode, pipelining, and compiler-visible structure.
Datapath	16/32-bit	General-purpose scalar datapaths broad enough for operating systems and richer address spaces.
Control Unit	Hardwired	Control is expressed directly in logic for speed and simplicity.
Execution Organization	Scalar Pipeline	One instruction enters per cycle while stages overlap.
Memory System	Direct Memory	The CPU largely waits on main memory or external bus timing.
Parallelism Topology	Scalar	One main stream of work dominates the processor.
Physical Implementation	Deep Submicron	High-frequency CMOS enables larger caches, prediction, and out-of-order structures.
Power and Thermal Regime	Embedded Deterministic	Predictable timing and low power dominate over speculative peak speed.
System Role	Embedded Control	Coordinates devices, sensors, interrupts, and real-time tasks.
Evidence Layer	Architectural Estimate	Known structure gives a plausible account without full validation.

RISC regularity is a technological commitment, not only a modeling convenience.

Embedded CPUs value predictability and energy discipline alongside speed.

A simple scalar pipeline is the reference point for understanding later overlap mechanisms.