mips - 1991 - evidence: ARCHITECTURAL_ESTIMATE

MIPS R4000

A 64-bit RISC workstation/server CPU that makes clean load-store design, deep pipelining, and cache hierarchy visible as technology choices.

Evidence source: martingallagher-code/modeling_2026/models/mips/mips_r4000

Technology Coordinates

Dimension	Value	Meaning
ISA Contract	RISC	Regular load/store instruction sets built for simple decode, pipelining, and compiler-visible structure.
Datapath	64-bit	Wide integer and address paths suited to large memory, servers, workstations, and modern clients.
Control Unit	Hardwired	Control is expressed directly in logic for speed and simplicity.
Execution Organization	Scalar Pipeline	One instruction enters per cycle while stages overlap.
Memory System	Private L2	A second near level filters misses before shared fabric or DRAM.
Parallelism Topology	Scalar	One main stream of work dominates the processor.
Physical Implementation	Deep Submicron	High-frequency CMOS enables larger caches, prediction, and out-of-order structures.
Power and Thermal Regime	Desktop Thermal	Boost and cooling determine how long peak clocks can be sustained.
System Role	General Purpose	Runs operating systems and varied applications.
Evidence Layer	Architectural Estimate	Known structure gives a plausible account without full validation.

The 64-bit CPU is partly an address-space technology.

Pipeline depth and cache assumptions define a processor's ideal workload.

RISC exposes the difference between architectural simplicity and system complexity.