intel - 2002 - evidence: ARCHITECTURAL_ESTIMATE

Intel Pentium 4 Northwood

The deep-pipeline frequency wager: a CPU technology organized around high clocks, aggressive prediction, and large penalties for wrong futures.

Evidence source: martingallagher-code/modeling_2026/models/intel/pentium_4_northwood

Technology Coordinates

Dimension	Value	Meaning
ISA Contract	x86 / CISC	Dense, historically layered instruction contracts with complex decode and deep backward compatibility.
Datapath	Renamed Physical Registers	Out-of-order cores map architectural names onto a larger physical register pool.
Control Unit	Deep Speculation	Large windows and deep pipelines make predicted futures central to throughput.
Execution Organization	Superscalar	Multiple operations can issue in a cycle when dependencies and resources permit.
Memory System	Private L2	A second near level filters misses before shared fabric or DRAM.
Parallelism Topology	Superscalar Core	Multiple issue slots live inside one core before scaling out to more cores.
Physical Implementation	Deep Submicron	High-frequency CMOS enables larger caches, prediction, and out-of-order structures.
Power and Thermal Regime	Desktop Thermal	Boost and cooling determine how long peak clocks can be sustained.
System Role	General Purpose	Runs operating systems and varied applications.
Evidence Layer	Architectural Estimate	Known structure gives a plausible account without full validation.

Clock frequency is a system-level bargain, not a free scalar improvement.

Branch prediction can become the guardian of the whole processor.

Thermal and power constraints can overturn an architectural fashion.