intel - 1971 - evidence: ARCHITECTURAL_ESTIMATE

Intel 4004

A 4-bit microprocessor showing the CPU as a new integrated control object: narrow datapath, small state, external memory, and board-level system role.

Evidence source: martingallagher-code/modeling_2026/models/intel/intel_4004

Technology Coordinates

Dimension	Value	Meaning
ISA Contract	Microcontroller ISA	Small embedded contracts optimized for control, interrupts, and deterministic peripheral interaction.
Datapath	4/8-bit	Small word machines where bus cycles, accumulator structure, and memory access dominate.
Control Unit	Hardwired	Control is expressed directly in logic for speed and simplicity.
Execution Organization	Multi-Cycle	Instructions reuse internal resources across phases before the next instruction completes.
Memory System	Direct Memory	The CPU largely waits on main memory or external bus timing.
Parallelism Topology	Scalar	One main stream of work dominates the processor.
Physical Implementation	Classic NMOS/CMOS	Early integrated microprocessors constrained by area, pins, and bus timing.
Power and Thermal Regime	Embedded Deterministic	Predictable timing and low power dominate over speculative peak speed.
System Role	Embedded Control	Coordinates devices, sensors, interrupts, and real-time tasks.
Evidence Layer	Architectural Estimate	Known structure gives a plausible account without full validation.

Technological Lessons

The CPU becomes a product category when control logic fits on one chip.

Pins, memory timing, and word width are architectural facts, not implementation trivia.

Early microprocessors reveal the processor as a system component before they reveal performance ambition.